-------------------------------------------------------------------------------
-- Title      : Top module of Nanocepter controller
-- Project    : 
-------------------------------------------------------------------------------
-- File       : nanocepterCtrl.vhd
-- Author     : Paul W
-- Company    : 
-- Created    : 2012-11-20
-- Last update: 2012-12-12
-- Platform   : 
-- Standard   : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top module for DRS Nanocepter radio controller using UART, VGA,
--              PMOD AD1
-------------------------------------------------------------------------------
-- Copyright (c) 2012 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2012-11-20  1.0      paul    Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;

library seg7;
library vgaController;
library components;
library uartRadio;

entity nanocepterCtrl is
  
  port (
    clk      : in  std_logic;
    buttons  : in  std_logic_vector(3 downto 0);
    switches : in  std_logic_vector(7 downto 0);
    ad1_d0   : in  std_logic;
    --RsRx     : in  std_logic;
    RsTx     : out std_logic;
    ad1_cs   : out std_logic;
    ad1_sclk : out std_logic;
    seg7     : out std_logic_vector(7 downto 0);
    anodes   : out std_logic_vector(3 downto 0);
    leds     : out std_logic_vector(7 downto 0);
    vgaRed   : out std_logic_vector(3 downto 1);
    vgaGreen : out std_logic_vector(3 downto 1);
    vgaBlue  : out std_logic_vector(3 downto 2);
    Hsync    : out std_logic;
    Vsync    : out std_logic
    );

end entity nanocepterCtrl;

architecture rtl of nanocepterCtrl is

  signal in_clk           : std_logic;
  signal in_rst           : std_logic;
  signal clk25            : std_logic;
  signal clk50Buf         : std_logic;
  signal clk40            : std_logic;
  signal one_ms_enable    : std_logic;
  signal buttonsDebounced : std_logic_vector(3 downto 0);
  signal mhzInt           : integer range 0 to 9999;
  signal khzInt           : integer range 0 to 9999;
  signal volInt           : integer range 0 to 99;
  signal detectionMode    : std_logic;
  signal bwsVal           : integer range 0 to 15;
  signal uartTx           : std_logic;
  signal audioData        : std_logic_vector(11 downto 0);
  signal audioDataEn      : std_logic;
  signal audioSampleEn    : std_logic;

begin  -- architecture rtl

  in_rst <= buttons(3);

  leds <= (others => '0');

  -- Map out the RS232 Tx
  RsTx <= uartTx;
  
  -- Input BUFG, needed with multiple DCMs
  BUFG_50_U : IBUFG
    port map (
      O => in_clk,                      -- Clock buffer output
      I => clk);                        -- Clock buffer input

  -- 25 MHz Internal feedback DCM. Assumes 50 MHz in from IBUFG
  -- This was created in coregen with CLKIN_IN considered an internal source
  vga25clk_U : entity vgaController.vga25clk
    port map (
      CLKIN_IN   => in_clk,
      RST_IN     => in_rst,
      CLKDV_OUT  => clk25,
      CLK0_OUT   => open,               -- Buffered CLKIN_IN
      LOCKED_OUT => open);              -- Base on feedback

  -- 40 MHz Internal feedback DCM. Assumes 50 MHz in from IBUFG
  -- This was created in coregen with CLKIN_IN considered an internal source
  vga40clk_U : entity vgaController.vga40clk
    port map (
      CLKIN_IN   => in_clk,
      RST_IN     => in_rst,
      CLKFX_OUT  => clk40,
      CLK0_OUT   => open,               -- Buffered CLKIN_IN
      LOCKED_OUT => open);              -- Base on feedback

  -- Tick module for debounce
  tickGen_U : entity components.tickGen
    generic map (
      INTERVAL => 50000)
    port map (
      in_clk   => in_clk,
      in_en    => '1',
      out_tick => one_ms_enable);

  --debounce                       
  debounceBits_U: entity components.debounceBits
    generic map (
      WIDTH => 4)
    port map (
      in_clk    => in_clk,
      in_sample => one_ms_enable,
      in_bits   => buttons,
      out_bits  => buttonsDebounced);

  -- Radio Control
  uartRadioCtrl_U : entity uartRadio.uartRadioCtrl
    port map (
      clk            => in_clk,
      rst            => in_rst,
      pushbuttons    => buttonsDebounced,
      sliderswitches => switches,
      mhz            => mhzInt,
      khz            => khzInt,
      vol            => volInt,
      det            => detectionMode,
      bws            => bwsVal,
      tx             => uartTx);

  -- Use a debounced push button to toggle sampling (allowing wave freeze)
  toggleSampling_proc : process (in_clk, in_rst) is
  begin  -- process toggleSampling_proc
    if in_rst = '1' then                -- asynchronous reset (active high)
      audioSampleEn <= '0';
    elsif rising_edge(in_clk) then      -- rising clock edge
      if buttonsDebounced(0) = '1' then
        audioSampleEn <= not audioSampleEn;
      end if;
    end if;
  end process toggleSampling_proc;
  
  -- Uses AD1 PMOD to sample audio @ 78.125 KSPS.
  -- Fifo outputs data in 50MHz domain.
  adcSampler_U : entity components.adcSampler
    port map (
      in_clk        => in_clk,
      in_rst        => in_rst,
      in_ad1_d0     => ad1_d0,
      in_getSamples => audioSampleEn,
      out_ad1_cs    => ad1_cs,
      out_ad1_sclk  => ad1_sclk,
      out_ad1Data   => audioData,
      out_ad1DataEn => audioDataEn);

  -- Displays all elements of VGA
  vgaLineDisplay_U : entity vgaController.vgaLineDisplay
    generic map (
      TEXT_COLOR => "11111111")
    port map (
      in_clk         => in_clk,
      in_clk25       => clk25,
      in_clk40       => clk40,
      in_rst         => in_rst,
      in_mhz         => mhzInt,
      in_khz         => khzInt,
      in_radioOnOff  => uartTx,
      in_radioVol    => volInt,
      in_radioDemod  => detectionMode,
      in_radioOutput => '0',
      in_radioBws    => bwsVal,
      in_audioData   => audioData(11 downto 4),
      in_audioDataEn => audioDataEn,
      in_backColor   => "00001001",
      out_vgaRed     => vgaRed,
      out_vgaGreen   => vgaGreen,
      out_vgaBlue    => vgaBlue,
      out_Hsync      => Hsync,
      out_Vsync      => Vsync);
  
  seg7Scanner_U : entity seg7.seg7Scanner
    port map (
      in_clk     => clk25, 
      in_rst     => in_rst,
      in_load    => '1',
      in_dig0    => x"E",
      in_dig1    => x"B",
      in_dig2    => x"A",
      in_dig3    => x"B",
      out_seg7   => seg7,
      out_anodes => anodes);

end architecture rtl;
